Digital communication receivers typically sample a received analog waveform and detect sampled data. In many data communication applications, Serializer and De-serializer (SERDES) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communication channel to the second point where it is received and converted from serial data to parallel data. As clock rates of the serial links increase to meet demand for higher data throughput, transmitted signals arriving at a receiver are increasingly susceptible to corruption by frequency-dependent signal loss of the channel, such as intersymbol interference (ISI), and other noise, such as crosstalk, echo, signal dispersion and distortion.
Receivers often equalize the channel to compensate for such signal degradation to correctly decode the received signals. For example, a receiver might apply equalization to the analog received signal using an analog front-end (AFE) equalizer that acts as a filter having parameters initially based on an estimate of the channel's features. Since, in many cases, little information about the channel transfer function is available during initial signal acquisition, and since the pulse transfer function can vary with time, an equalizer with adaptive setting of parameters providing adjustable range might be employed to mitigate the degradation of the signal transmitted through the channel. Thus, once the signal is received, the analog filter parameters might be adapted based on information derived from the received analog signal.
A decision-feedback equalizer (DFE) is often used to remove ISI and other noise to determine a correct bit sequence from the received signal, and is often employed in conjunction with an AFE. Generally, a traditional DFE utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously decided symbols from the received signal. Thus, a DFE typically determines a correct logic value of a given sample (“cursor value”) of the input signal for a given symbol period in the presence of ISI based on one or more previous logic values (“pre-cursor values”). For example, a traditional DFE might subtract the sum of ISI contributions for a predetermined number of previously decoded symbols of the received signal. The ISI contributions might be determined by multiplying the previously decoded symbol values by their corresponding pulse response coefficients (“taps”) of the communication channel. These products might be summed and subtracted from the received signal. Analog DFEs are generally capable of high bandwidth operation, but both power consumption and semiconductor area increase as the bandwidth increases.
Another type of DFE is an unrolled DFE such as described in U.S. Published Patent Application 2009/0304066, filed on Jun. 6, 2008 to Chmelar et al. (hereinafter “Chmelar”), which is incorporated by reference herein. For example, in the unrolled DFE of Chmelar, the feedback path is removed between the analog and digital domains that exists for a traditional DFE (e.g., the feedback path between the DFE and the AFE). The unrolled DFE precomputes the possible ISI contributions based on the received symbol history based on a first speculation that the result from processing the succeeding bit (i.e., a decision output) will be logic ‘1’ and a second speculation that the result from processing the succeeding bit will be logic ‘0’. Once the result from the succeeding bit is available, the pre-calculated adjustment feedback value corresponding to the correctly speculated output value is selected to process the following input bits. In this way, latency between determination of a succeeding bit and providing a data dependent input for processing a following bit can be greatly reduced as the time required to perform adjustment calculations is effectively eliminated from the latency.
However, there are limitations of traditional DFEs and unrolled DFEs. For example, in both traditional and unrolled DFEs, pre-cursor ISI cannot be equalized since a DFE is a causal system and for a DFE to recover a symbol and feedback its ISI contribution to equalize the received signal, the symbol must have already been received and a DFE does not predict future symbols. This is an unfortunate limitation since both future symbols (pre-cursor) and past symbols (post-cursor) contribute to ISI. Although pre-cursor ISI was negligible at lower baud rates, as baud rates have increased to tens of gigabits per second through channels whose transmission properties have not improved proportionally, unequalized pre-cursor ISI has become increasingly significant in degrading the Bit Error Ratio (BER) of the system.
Further, a traditional DFE is limited to performing the ISI determination and subtraction in a single symbol period (a “unit interval” or UI). The UI is the baud rate of the SERDES channel, which can be in excess of 12 Gbps. This single UI timing requirement (“DFE iteration bound”) dictates the maximum frequency at which the DFE can operate. To meet the DFE iteration bound at high baud rates, drive strength of some analog circuitry might be increased, which undesirably increases power consumption of the receiver. In an unrolled DFE, although the feedback between the AFE and the DFE is removed, the single UI iteration bound still limits the operation of the DFE. Further, unrolled DFEs might experience data recovery latency and exponential scaling of circuit complexity and power consumption with respect to ISI. Larger data recovery latency slows down the timing recovery loop of the receiver, thereby affecting the receiver's ability to extract and effectively track the transmitter's clock phase and frequency. The slowed timing loop sacrifices some tolerance to jitter in the received signal, which directly affects BER. Thus, it is beneficial that a SERDES receiver recover the transmitted symbols as quickly as possible to enable a fast timing recovery loop.